SH7040 Datasheet, PDF (113/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

CPU returns to ordinary program execution state through the exception processing state after the
oscillator stabilization time has elapsed. In this mode, power consumption drops markedly, since
the oscillator stops (table 2.18).
Table 2.18 Power-Down State
State
Mode
Transition
Conditions
On-Chip
Peripheral CPU
Clock CPU Modules Registers
On-Chip
Cache or I/O
On-Chip Port
RAM
Pins
Sleep
Execute Run
SLEEP
instruction
with SBY bit
cleared to 0
in SBYCR
Halt Run
Held
Held
Held
Canceling
• Interrupt
• DMA address
error
• Power-on reset
• Manual reset
Stand- Execute Halt
by SLEEP
instruction
with SBY bit
set to 1 in
SBYCR
Halt Halt and
initialize^*
Held
Held
Note: * Differs depending on the peripheral module and pin.
Held or •
Hi-Z
(select-
•
able) ^•
NMI interrupt
Power-on reset
Manual reset
75