SH7040 Datasheet, PDF (242/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

to cause the external device to negate the BREQ and return the bus rights to the SH7040 Series.
Please note that if the external device does not return the bus rights within the time prescribed for
the DRAM refresh interval, this LSI will not be able to perform the refresh operation and the
DRAM contents cannot be guaranteed.
Figure 10.22 shows the bus right release procedure.
SH704X
BREQ accepted
BREQ = Low
External device
Bus right request
Strobe pin:
high-level output
Address, data,
strobe pin:
high impedance
Bus right release
response
BACK confirmation
BACK = Low
Bus right release status
Bus right acquisition
Figure 10.22 Bus Right Release Procedure
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