SH7040 Datasheet, PDF (318/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.1.4 Register Configuration
Table 12.3 summarizes the MTU register configuration.
Table 12.3 Register Configuration
Chan-
nel Name
Abbrevi-
ation R/W
Initial
Value
Shared Timer start register
TSTR R/W H'00
Timer synchro register
TSYR R/W H'00
0
Timer control register 0
TCR0 R/W H'00
Timer mode register 0
TMDR0 R/W H'C0
Timer I/O control register 0H TIOR0H R/W H'00
Timer I/O control register 0L TIOR0L R/W H'00
Timer interrupt enable
register 0
TIER0 R/W H'40
Timer status register 0
TSR0 R/(W)^*2 H'C0
Timer counter 0
TCNT0 R/W H'0000
General register 0A
TGR0A R/W H'FFFF
General register 0B
TGR0B R/W H'FFFF
General register 0C
TGR0C R/W H'FFFF
General register 0D
TGR0D R/W H'FFFF
1
Timer control register 1
TCR1 R/W H'00
Timer mode register 1
TMDR1 R/W H'C0
Timer I/O control register 1 TIOR1 R/W H'00
Timer interrupt enable
register 1
TIER1 R/W H'40
Timer status register 1
TSR1 R/(W)^*2 H'C0
Timer counter 1
TCNT1 R/W H'0000
General register 1A
TGR1A R/W H'FFFF
General register 1B
TGR1B R/W H'FFFF
Address
H'FFFF8240
H'FFFF8241
H'FFFF8260
H'FFFF8261
H'FFFF8262
H'FFFF8263
H'FFFF8264
H'FFFF8265
H'FFFF8266
H'FFFF8268
H'FFFF826A
H'FFFF826C
H'FFFF826E
H'FFFF8280
H'FFFF8281
H'FFFF8282
H'FFFF8284
H'FFFF8285
H'FFFF8286
H'FFFF8288
H'FFFF828A
Access Size
(Bits) ^*1
8, 16, 32
16, 32
8, 16, 32
16, 32
280