SH7040 Datasheet, PDF (656/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

18.3.6 Port B Control Registers (PBCR1 and PBCR2)
PBCR1 and PBCR2 are 16-bit read/write registers that select the functions of the ten multiplexed
pins of port B. PBCR1 selects the functions of the top two bits of port B; PBCR2 selects the
functions of the bottom eight bits of port B.
Port B has bus control signals (RDWR, RAS, CASH, CASL, WAIT, BREQ, BACK) and address
outputs (A21, A20, A19, A18, A17, A16), but there are instances when the register settings that
select these pin functions will be ignored, depending on the operation mode. Refer to table 18.2,
Pin Arrangement by Mode, for details.
PBCR1 and PBCR2 are both initialized to H'0000 by external power-on reset but are not
initialized for manual resets, reset by WDT, standby mode, or sleep mode, so the previous data is
maintained.
Port B Control Register 1 (PBCR1):
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
PB9 PB9 PB8 PB8
MD1 MD0 MD1 MD0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
• Bits 15-4—Reserved: These bits always read as 0. The write value should always be 0.
• Bits 3 and 2—PB9 Mode (PB9MD1 and PB9MD0): PB9MD1 and PB9MD0 select the
function of the PB9/IRQ7/A21/ADTRG pin.
Bit 3: PB9MD1
0
1
Bit 2: PB9MD0
0
1
0
1
Description
General input/output (PB9) (initial value)
Interrupt request input (IRQ7)
Address output (A21) (PB9 in single chip mode)
A/D conversion trigger input (ADTRG)
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