SH7040 Datasheet, PDF (589/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

ADF
ADST
Set to 1 by software
Channel 0
Conversion Sampling
standby
1
A/D
conversion
1
Conversion
standby
Automatic clear
Channel 1
Conversion standby
Sampling
2
A/D
conversion
2
Conversion standby
Channel 2 ^{Conversion standby}
Sampling
3
A/D
conversion
3
Conversion
standby
Channel 3 Conversion standby
ADDRA
Conversion result 1
ADDRB
Conversion result 2
ADDRC
Conversion result 3
ADDRD
Figure 15.6 A/D Converter Operation Example (Group-Single Mode)
15.4.4 Group-Scan Mode
Choose group-scan mode when doing repeated A/D conversions for multiple channels. This is
useful when doing continuous monitoring of the analog inputs of multiple channels.
When the ADST bit is set to 1, A/D conversion is started according to the designated conversion
start conditions. The ADST bit is held to 1 until 0 cleared by software. A/D conversion for the
selected input channels is repeated during that interval.
The ADF flag is set to 1 at the completion of the first conversions of all the designated input
channels. At this point, if the ADIE bit is set to 1, an ADI interrupt request is issued, and the A/D
converter is temporarily halted. With the A/D converter in stop mode due to an ADI interrupt
request, conversion is restarted when the ADF flag is cleared to 0. The ADF flag is cleared by
reading the ADCSR, then writing a 0.
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