SH7040 Datasheet, PDF (540/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 14.8 Serial Mode Register Settings and SCI Communication Formats
SMR Settings
SCI Communication Format
Mode
Bit 7 Bit 6 Bit 5 Bit 2 Bit 3 Data Parity Multipro- Stop Bit
C/A CHR PE MP STOP Length Bit
cessor Bit Length
Asynchronous 0 0
0
0
0
8-bit
Not set Not set 1 bit
1
2 bits
1
0
Set
1 bit
1
2 bits
1
0
0
7-bit
Not set
1 bit
1
2 bits
1
0
Set
1 bit
1
2 bits
Asynchronous
(multiprocessor
format)
0
*
1
0
*
1
1
*
0
8-bit
Not set Set
7-bit
1 bit
2 bits
1 bit
*
1
2 bits
Clock
1*
*
*
*
8-bit
synchronous
Not set None
Note: Asterisks (*) in the table indicate don’t-care bits.
Table 14.9 SMR and SCR Settings and SCI Clock Source Selection
SMR SCR Settings
SCI Transmit/Receive Clock
Mode
Bit 7 Bit 1 Bit 0
C/A CKE1 CKE0 Clock Source SCK Pin Function^*
Asynchronous 0
0
0
Internal
SCI does not use the SCK pin
1
Outputs a clock with frequency
matching the bit rate
1
0
External
Inputs a clock with frequency 16 times
the bit rate
1
Clock synch- 1
0
0
ronous
1
Internal
Outputs the synchronous clock
1
0
External
Inputs the synchronous clock
1
Note: * Select the function in combination with the pin function controller (PFC).
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