SH7040 Datasheet, PDF (146/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

6.3 Description of Registers
6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH)
Interrupt priority registers A–H (IPRA–IPRH) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts.
Correspondence between interrupt request sources and each of the IPRA–IPRH bits is shown in
table 6.4.
Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 6.4 Interrupt Request Sources and IPRA–IPRH
Bits
Register
15–12
11–8
7–4
3–0
Interrupt priority register A
IRQ0
IRQ1
IRQ2
IRQ3
Interrupt priority register B
IRQ4
IRQ5
IRQ6
IRQ7
Interrupt priority register C
DMAC0
DMAC1 DMAC2
DMAC3
Interrupt priority register D
MTU0
MTU0 MTU1
MTU1
Interrupt priority register E
MTU2
MTTU2 MTU3
MTU3
Interrupt priority register F
MTU4
MTU4 SCI0
SCI1
Interrupt priority register G
A/D(A/D0,
A/D1)^*
DTC
CMT0
CMT1
Interrupt priority register H
WDT, BSC I/O
Reserved Reserved
Note: * Excluding A mask products are A/D, A mask products are A/D0 and A/D1.
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