 English |
|
|
|
|
|
|
|
| SH7040 Datasheet, PDF (832/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2) | |||
| |||
| ◁ |
Tp
Tr
Tc1
Tc2
CK
A21âA0
RAS
CASxx
(During read)
RDWR
(During read)
D31â D0
(During read)
CASxx
(During write)
RDWR
(During write)
D31âD0
(During write)
DACKn
RD
(During read)
WRxx
(During write)
tAD
tAD
Row address
tASR
tRASD1
tRAH
tRP
Column address
tRASD2
tCASD1
tCASD2
tRAC
tCAC
tAA
tRDS
tRDH
tCASD1
tRWD1
tDS
tWDD
tDACKD1
tCASD2
tRWD2
tDH
tWDH
tDACKD1
tRSD1
tRSD2
tWSD1
tWSD2
Note: tRDH is specified from fastest negate timing of A21âA0, RAS, and CAS.
Figure 26.11 DRAM Cycle (Normal Mode, No Wait, TPC = 0, RCD = 0)
794
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese