SH7040 Datasheet, PDF (106/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 2.14 Logic Operation Instructions
Instruction
Instruction Code
Operation
Execu-
tion
Cycles T Bit
AND Rm,Rn
0010nnnnmmmm1001 Rn & Rm → Rn
1
—
AND #imm,R0
11001001iiiiiiii R0 & imm → R0
1
—
AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm → 3
—
(R0 + GBR)
NOT Rm,Rn
0110nnnnmmmm0111 ~Rm → Rn
1
—
OR Rm,Rn
0010nnnnmmmm1011 Rn | Rm → Rn
1
—
OR #imm,R0
11001011iiiiiiii R0 | imm → R0
1
—
OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm →
3
—
(R0 + GBR)
TAS.B @Rn
0100nnnn00011011
If (Rn) is 0, 1 → T; 1 → 4
MSB of (Rn)^*
Test
result
TST Rm,Rn
0010nnnnmmmm1000
Rn & Rm; if the result is 1
0, 1 → T
Test
result
TST #imm,R0
11001000iiiiiiii
R0 & imm; if the result is 1
0, 1 → T
Test
result
TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm; if 3
the result is 0, 1 → T
Test
result
XOR Rm,Rn
0010nnnnmmmm1010 Rn ^ Rm → Rn
1
—
XOR #imm,R0
11001010iiiiiiii R0 ^ imm → R0
1
—
XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm → 3
—
(R0 + GBR)
Note: * The on-chip DMAC/DTC bus cycles are not inserted between the read and write cycles of
TAS instruction execution. However, bus release due to BREQ is carried out.
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