SH7040 Datasheet, PDF (503/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

13.3.4 Timing of Setting the Overflow Flag (OVF)
In the interval timer mode, when the TCNT overflows, the OVF flag of the TCSR is set to 1 and
an interval timer interrupt is simultaneously requested (figure 13.6).
CK
TCNT
H'FF H'00
Overflow signal
(internal signal)
OVF
Figure 13.6 Timing of Setting the OVF
13.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When the TCNT overflows in the watchdog timer mode, the WOVF bit of the RSTCSR is set to 1
and a WDTOVF signal is output. When the RSTE bit is set to 1, TCNT overflow enables an
internal reset signal to be generated for the entire chip (figure 13.7).
CK
TCNT
Overflow signal
(internal signal)
H'FF H'00
WOVF
Figure 13.7 Timing of Setting the WOVF Bit
465