SH7040 Datasheet, PDF (93/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 2.8 Addressing Modes and Effective Addresses (cont)
Addressing
Mode
PC relative
addressing
Instruction
Format Effective Addresses Calculation
disp:8
The effective address is the PC value sign-extended
with an 8-bit displacement (disp), doubled, and
added to the PC value.
Equation
PC + disp × 2
PC
disp
+
(sign-extended)
×
PC + disp × 2
disp:12
2
The effective address is the PC value sign-extended PC + disp × 2
with a 12-bit displacement (disp), doubled, and
added to the PC value.
PC
disp
+
(sign-extended)
×
PC + disp × 2
2
Rn
The effective address is the register PC value
PC + Rn
plus Rn.
PC
+
PC + Rn
Immediate
addressing
#imm:8
#imm:8
#imm:8
Rn
The 8-bit immediate data (imm) for the TST, AND, —
OR, and XOR instructions are zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD, —
and CMP/EQ instructions are sign-extended.
The 8-bit immediate data (imm) for the TRAPA
—
instruction is zero-extended and is quadrupled.
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