SH7040 Datasheet, PDF (91/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 2.8 Addressing Modes and Effective Addresses (cont)
Addressing
Mode
Instruction
Format
Effective Addresses Calculation
Indirect register
addressing with
displacement
@(disp:4,
Rn)
The effective address is Rn plus a 4-bit
displacement (disp). The value of disp is zero-
extended, and remains the same for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
Rn
disp
(zero-extended)
+
×
Rn + disp × 1/2/4
Equation
Byte: Rn +
disp
Word: Rn +
disp × 2
Longword: Rn
+ disp × 4
1/2/4
Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0.
register
addressing
Rn
+
Rn + R0
Rn + R0
R0
Indirect GBR
addressing with
displacement
@(disp:8,
GBR)
The effective address is the GBR value plus an
8-bit displacement (disp). The value of disp is zero-
extended, and remains the same for a byte opera-
tion, is doubled for a word operation, and is
quadrupled for a longword operation.
GBR
disp
+
(zero-extended)
×
GBR
+ disp × 1/2/4
Byte: GBR +
disp
Word: GBR +
disp × 2
Longword:
GBR + disp ×
4
1/2/4
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