SH7040 Datasheet, PDF (14/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Section
25.2 DC
Characteristics
Table 25.2 DC
Characteristics
25.3.2 Control
Signal Timing
Table 25.5 Control
Signal Timing
Page
751
754
25.3.3 Bus Timing 763
Figure 25.12 DRAM
Cycle (Normal Mode,
1 Wait, TPC=0,
RCD=0)
Description
Note amended
*2 5 mA in the A mask version, except for F-ZTAT products.
Note amended
Note: * The RES, MRES, NMI, BREQ, and IRQ7–IRQ0 signals are
asynchronous inputs, but when thesetup times shown here
are provided, the signals are considered to have produced
changes at clock rise (for RES, MRES, BREQ) or clock fall
(for NMI and IRQ7–IRQ0). If the setup times are not
provided, recognition is delayed until the next clock rise or
fall.
Figure amended
Tcw1
Tc2
Column address
t_CASD1
t_CAC
t_AA
t_RAC
t_RDS
Figure 25.13 DRAM 764
Cycle (Normal Mode,
2 Waits, TPC=1,
RCD=1)
Figure amended
Tcw1
Tcw2
Column address
t_CASD1
t_CAC
t_AA