SH7040 Datasheet, PDF (104/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 2.13 Arithmetic Operation Instructions (cont)
Instruction
DMULS.L Rm,Rn
Instruction Code
0011nnnnmmmm1101
DMULU.L Rm,Rn
0011nnnnmmmm0101
DT
Rn
0100nnnn00010000
EXTS.B Rm,Rn
0110nnnnmmmm1110
EXTS.W Rm,Rn
0110nnnnmmmm1111
EXTU.B Rm,Rn
0110nnnnmmmm1100
EXTU.W Rm,Rn
0110nnnnmmmm1101
MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
MUL.L Rm,Rn
MULS.W Rm,Rn
0000nnnnmmmm0111
0010nnnnmmmm1111
MULU.W Rm,Rn
0010nnnnmmmm1110
NEG
NEGC
Rm,Rn
Rm,Rn
0110nnnnmmmm1011
0110nnnnmmmm1010
Operation
Execu-
tion
Cycles T Bit
Signed operation of Rn 2 to 4^* —
× Rm → MACH, MACL
32 × 32 → 64 bit
Unsigned operation of 2 to 4^* —
Rn × Rm → MACH,
MACL 32 × 32 → 64 bit
Rn – 1 → Rn, when Rn 1
is 0, 1 → T. When Rn is
nonzero, 0 → T
Comparison
result
A byte in Rm is sign- 1
—
extended → Rn
A word in Rm is sign- 1
—
extended → Rn
A byte in Rm is zero- 1
—
extended → Rn
A word in Rm is zero- 1
—
extended → Rn
Signed operation of
3/(2 to —
(Rn) × (Rm) + MAC → 4)^*
MAC 32 × 32 → 64 bit
Signed operation of
3/(2)^* —
(Rn) × (Rm) + MAC →
MAC 16 × 16 + 64 →
64 bit
Rn × Rm → MACL, 32 2 to 4^* —
× 32 → 32 bit
Signed operation of Rn 1 to 3^* —
× Rm → MAC 16 × 16
→ 32 bit
Unsigned operation of
Rn × Rm → MAC 16 ×
16 → 32 bit
1 to 3^* —
0–Rm → Rn
1
—
0–Rm–T → Rn, Borrow 1
→T
Borrow
66