SH7040 Datasheet, PDF (827/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

26.3.3 Bus Timing
Table 26.6 Bus Timing (Conditions: V_CC = 3.0^*1 to 3.6V, AV_CC = 3.0^*1 to 3.6V, AV_CC = V_CC
± 10%, AV_ref = 3.0^*1 to AV_CC, V_SS = AV_SS = 0V, T_a = –20 to +75°C)
Item
Symbol Min
Max Unit Figure
Address delay time
CS delay time 1
CS delay time 2
Read strobe delay time 1
Read strobe delay time 2
Read data setup time
Read data hold time
Write strobe delay time 1
Write strobe delay time 2
Write data delay time
Write data hold time
WAIT setup time
WAIT hold time
RAS delay time 1
RAS delay time 2
CAS delay time 1
CAS delay time 2
Read data access time
Access time from read strobe
Access time from column
address
t_AD
t_CSD1
t_CSD2
t_RSD1
t_RSD2
t_RDS^*5
t_RDH
t_WSD1
t_WSD2
t_WDD
t_WDH
t_WTS
t_WTH
t_RASD1
t_RASD2
t_CASD1
t_CASD2
t_ACC^*2
t_OE^*2
t_AA^*2
3^*4
3^*4
3^*4
3^*4
3^*4
25
0
3^*4
3^*5
—
0
15
0
3^*4
3^*4
3^*4
3^*4
t_cyc× (n+2) – 45
t_cyc× (n+1.5) – 40
t_cyc× (n+2) – 45
35 ns
35 ns
35 ns
35 ns
35 ns
— ns
— ns
35 ns
35 ns
45 ns
25^*3 ns
— ns
— ns
35 ns
35 ns
35 ns
35 ns
— ns
— ns
— ns
26.8, 9, 11–16, 19
26.8, 9, 19
26.8, 9, 11–16, 19
26.10,15, 19
26.11–18
26.8, 9
26.11–16
Access time from RAS
Access time from CAS
t_RAC^*2
t_CAC^*2
t_cyc× (n+RCD+2.5) – 40 — ns
t_cyc× (n+1) – 40
— ns
Row address hold time
t_RAH
t_cyc× (RCD+0.5) – 15 — ns
Row address setup time
t_ASR
0
— ns
Data input setup time
t_DS
t_cyc× (m+0.5) – 27
— ns
Data input hold time
t_DH
20
— ns
Notes: n is the wait number. m is 1 unless the DRAM write cycle wait number is 0, then m is 0.
RCD is the set value of the RCD bit of DCR.
*1 SH7042/43 ZTAT (excluding A mask) are 3.2V.
*2 If the access time is satisfied, then the t_RDS need not be satisfied.
*3 t_WDH (max) is a reference value.
*4 The delay time min values are reference values (typ).
*5 t_RDS is a reference value.
789