SH7040 Datasheet, PDF (13/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Section
Page Description
22.7.4 Erase-Verify ⁷¹³
Mode
Figure amended
Start
*1
Figure 22.14
Erase/Erase-Verify
Flowchart
Set SWE bit in FLMCR1
Wait 10 µs
*5
n=1
Set EBR1(2)
*3
Enable WDT
Set ESU1(2) bit in FLMCR1(2)
Wait 200 µs
Set E1(2) bit in FLMCR1(2)
*5
Start erase
Wait 5 ms
*5
Clear E1(2) bit in FLMCR1(2)
Halt erase
Wait 10 µs
*5
Clear ESU1(2) bit in FLMCR1(2)
Wait 10 µs
*5
Disable WDT
Set EV1(2) bit in FLMCR1(2)
Wait 20 µs
*5
Set block start address to verify address
n←n+1
24.4.2 Canceling the 747
Standby Mode
H'FF dummy write to verify address
Wait 2 µs
*5
Increment
address
NG
Read verify data
*2
NG
Verify data = all "1"?
OK
Last address of block?
OK
Clear EV1(2) bit in FLMCR1(2)
Clear EV1(2) bit in FLMCR1(2)
Wait 5 µs
*5
NG
*4
End of
erasing of all erase
blocks?
OK
Clear SWE bit in FLMCR1
Wait 5 µs
*5
*5
NG
n ≥ 60?
OK
Clear SWE bit in FLMCR1
End of erasing
Erase failure
Notes: *1 Preprogramming (setting erase block data to all “0”) is not necessary.
*2 Verify data is read in 32-bit (longword) units.
*3 Set only one bit in EBR1(2). More than one bit cannot be set.
*4 Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
*5 Make sure to set the wait times and repetitions as specified. Erasing may not complete correctly if values other
than the specified ones are used.
Cancellation by a Manual Reset deleted
25. Electrical
—
Characteristics (5V,
33.3 MHz Version)
Deleted