SH7040 Datasheet, PDF (149/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bits 7–0—IRQ0–IRQ7 Flags (IRQ0F–IRQ7F): These bits display the IRQ0–IRQ7 interrupt
request status.
Bits 7-0:
IRQ0F–IRQ7F
0
1
Detection Setting
Level detection
Edge detection
Level detection
Edge detection
Description
No IRQn interrupt request exists.
Clear conditions: When IRQn input is high level
No IRQn interrupt request was detected. (initial value)
Clear conditions:
1. When a 0 is written after reading IRQnF = 1 status
2. When IRQn interrupt exception processing has been
executed
3. When a DTC transfer due to IRQn interrupt has been
executed
An IRQn interrupt request exists.
Set conditions: When IRQn input is low level
An IRQn interrupt request was detected.
Set conditions: When a falling edge occurs at an IRQn input
ISR.IRQnF
IRQnS
(0: level,
1: edge)
IRQ pin
Level
detection
Edge
detection
RESIRQn
SQ
Selection
R
DTC
Judgment
DTC
activation
request
CPU
interrupt
request
(IRQn interrupt acceptance/DTC transfer completion/IRQnF = 0 write after IRQnF = 1 read)
Figure 6.2 External Interrupt Process
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