SH7040 Datasheet, PDF (76/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 1.7 Pin Functions (cont)
Classification
Operating
mode control
Symbol I/O
MD0–MD3 I
FWP
I
Interrupts
NMI
I
IRQ0–
I
IRQ7
IRQOUT O
Address bus
Data bus
Bus control
A0–A21 O
D0–D15 I/O
(QFP-112)
D0–D31
(QFP-144)
CS0–CS3 O
RD
O
WRH
O
WRL
O
WAIT
I
RAS
O
CASH
O
Name
Mode set
Flash memory
write protect
Non-maskable
interrupt
Interrupt
requests 0–7
Interrupt request
output
Address bus
Data bus
Function
Determines the operating mode. Do
not change input value during
operation.
Protects flash memory from being
written or deleted.
Non-maskable interrupt request pin.
Enables selection of whether to
accept on the rising or falling edge.
Maskable interrupt request pins.
Allows selection of level input and
edge input.
Indicates that interrupt cause has
occurred. Enables notification of
interrupt generation also during bus
release.
Outputs addresses.
16-bit (QFP-112 pin and TQFP-120
pin versions) or 32-bit (QFP-144 pin
version) bidirectional data bus.
Chip selects 0–3
Read
Upper write
Lower write
Wait
Row address
strobe
Upper column
address strobe
Chip select signals for external
memory or devices.
Indicates reading from an external
device.
Indicates writing the upper 8 bits
(15–8) of external data.
Indicates writing the lower 8 bits
(7–0) of external data.
Input causes insertion of wait cycles
into the bus cycle during external
space access.
Timing signal for DRAM row
address strobe.
Timing signal for DRAM column
address strobe.
Output when the upper 8 bits of
data are accessed.
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