SH7040 Datasheet, PDF (521/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

14.2.8 Bit Rate Register (BRR)
The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write the BRR. The BRR is initialized to H'FF by a power-on reset
or in standby mode. Each channel has independent baud rate generator control, so different values
can be set in the two channels. Manual reset does not initialize BRR.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 14.3 lists examples of BRR settings in the asynchronous mode; table 14.4 lists examples of
BBR settings in the clock synchronous mode.
Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode
Bit Rate
(Bits/s)
110
150
300
600
1200
2400
4800
9600
14400
19200
28800
31250
38400
4
n N Error (%)
2 70 0.03
1 207 0.16
1 103 0.16
0 207 0.16
0 103 0.16
0 51 0.16
0 25 0.16
0 12 0.16
0 8 –3.55
0 6 –6.99
0 3 8.51
0 3 0.00
0 2 8.51
φ (MHz)
4.9152
n N Error (%)
2 86 0.31
1 255 0.00
1 127 0.00
0 255 0.00
0 127 0.00
0 63 0.00
0 31 0.00
0 15 0.00
0 10 –3.03
0 7 0.00
0 4 6.67
0 4 –1.70
0 3 0.00
6
n N Error (%)
2 106 –0.44
2 77 0.16
1 155 0.16
1 77 0.16
0 155 0.16
0 77 0.16
0 38 0.16
0 19 –2.34
0 12 0.16
0 9 –2.34
0 6 –6.99
0 5 0.00
0 4 –2.34
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