SH7040 Datasheet, PDF (161/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

UBAMRL:
Bit: 15
14
13
12
11
10
UBAMRL UBM15 UBM14 UBM13 UBM12 UBM11 UBM10
Initial value: 0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W
9
UBM9
0
R/W
8
UBM8
0
R/W
Bit:
UBAMRL
Initial value:
R/W:
7
UBM7
0
R/W
6
UBM6
0
R/W
5
UBM5
0
R/W
4
UBM4
0
R/W
3
UBM3
0
R/W
2
UBM2
0
R/W
1
UBM1
0
R/W
0
UBM0
0
R/W
• UBAMRH Bits 15–0—User Break Address Mask 31–16 (UBM31–UBM16): These bits
designate whether to mask any of the break address 31–16 bits (UBA31–UBA16) established
in the UBARH.
• UBAMRL Bits 15–0—User Break Address Mask 15–0 (UBM15–UBM0): These bits
designate whether to mask any of the break address 15–0 bits (UBA15–UBA0) established in
the UBARL.
Bits 15–0: UBMn
0
1
Note: n = 31–0
Description
Break address UBAn is included in the break conditions (initial value)
Break address UBAn is not included in the break conditions
7.2.3 User Break Bus Cycle Register (UBBR)
User break bus cycle register (UBBR) is a 16-bit readable/writable register that selects from
among the following four break conditions:
1. CPU cycle/ DMAC/DTC cycle
2. Instruction fetch/data access
3. Read/write
4. Operand size (byte, word, longword)
Resets and hardware standbys initialize the UBBR to H'0000. It is not initialized in software
standby mode.
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