SH7040 Datasheet, PDF (742/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

22.7 Programming/Erasing Flash Memory
A software method, using the CPU, is employed to program and erase flash memory in the on-
board programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by
setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1 for addresses H'00000–H'1FFFF,
or the PSU2, ESU2, P2, E2, PV2, and EV2 bits in FLMCR2 for addresses H'20000–H'3FFFF.
The flash memory cannot be read while being programmed or erased. Therefore, the program
(programming control program) that controls flash memory programming/erasing should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU1, PSU1, EV1, PV1,
E1, and P1 bits in FLMCR1, or the ESU2, PSU2, EV2, PV2, E2, and P2 bits in
FLMCR2, is executed by a program in flash memory.
2. When programming or erasing, set FWP to low level (programming/erasing will not be
executed if FWP is set to high level).
3. Programming should be performed in the erased state. Do not perform additional
programming on previously programmed addresses.
4. Do not program addresses H'00000–H'1FFFF and H'20000–H'3FFFF simultaneously.
Operation is not guaranteed if this is done.
22.7.1 Program Mode (n = 1 for Addresses H'0000–H'1FFFF, n = 2 for Addresses
H'20000–H'3FFFF)
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figure 22.13 should be followed. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a
time.
Following the elapse of 10 µs or more after the SWE bit is set to 1 in flash memory control
register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data
area, and the 32-byte data in the program data area in RAM is written consecutively to the
program address (the lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60,
H'80, H'A0, H'C0, or H'E0). Thirty-two consecutive byte data transfers are performed. The
program address and program data are latched in the flash memory. A 32-byte data transfer must
be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the
extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set a minimum value of 300 µs or more as the WDT overflow period. After this, preparation for
program mode (program setup) is carried out by setting the PSUn bit in FLMCRn, and after the
elapse of 50 µs or more, the operating mode is switched to program mode by setting the Pn bit in
704