SH7040 Datasheet, PDF(707/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (707/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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Section 21 128kB PROM

21.1 Overview

This LSI has 128 kbytes of on-chip PROM.The on-chip ROM is connected to the CPU, the direct

memory access controller (DMAC) and the data transfer controller (DTC) through a 32-bit data

bus (figures 21.1). The CPU, DMAC, and DTC can access the on-chip ROM in 8, 16, and 32-bit

widths. Data in the on-chip ROM can always be accessed in one cycle.

Internal data bus (32 bits)

H'00000000

H'00000004

H'00000001

H'00000005

H'00000002

H'00000006

H'00000003

H'00000007

On-chip ROM

H'0001FFFC

H'0001FFFD

H'0001FFFE

H'0001FFFF

Figure 21.1 PROM Block Diagram

The operating mode determines whether the on-chip ROM is valid or not. The operating mode is

selected using mode-setting pins MD3âMD0 as shown in table 21.1. If you are using the on-chip

ROM, select mode 2 or mode 3; if you are not, select mode 0 or 1. The on-chip ROM is allocated

to addresses H'00000000âH'0001FFFF of memory area 0.

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