SH7040 Datasheet, PDF (223/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

10.3 Accessing Ordinary Space
A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM
direct connections.
10.3.1 Basic Timing
Figure 10.3 shows the basic timing of ordinary space accesses. Ordinary access bus cycles are
performed in 2 states.
T₁
T₂
CK
Address
Read
CSn
RD
Data
Write
WRx
Data
Figure 10.3 Basic Timing of Ordinary Space Access
During a read, irrespective of operand size, all bits in the data bus width for the access space
(address) are fetched by the LSI on RD, using the required byte locations.
During a write, the following signals are associated with transfer of these actual byte locations:
WRHH (bits 31–24), WRHL (bits 23–16), WRH (bits 15–8), and WRL (bits 7–0).
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