SH7040 Datasheet, PDF (613/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

16.3 Interface with CPU
Although A/D data register ADDR (ADDRA0–ADDRD0, ADDRA1–ADDRD1) are 16-bit
registers, the bus width within the chip that integrates with the CPU is 8-bits. So, upper and lower
data of the ADDR must be read separately.
To avoid change in data while reading the upper/lower 2 bytes of ADDR, the lower byte data is
read through the temporary register (TEMP). The upper byte data can be read directly.
The procedure for reading data from ADDR is as follows: First, read the upper byte data from
ADDR. At this time, the upper byte data is read directly into the CPU and the lower byte data is
transferred to TEMP of the mid-speed A/D converter. Next, read the lower byte to read the TEMP
contents into the CPU.
When reading the ADDR in byte size, read the upper byte before the lower byte. Furthermore, it is
possible to read only the upper byte, however, please note that contents are not guaranteed when
reading only the lower byte. In addition, when reading ADDR in word size, upper byte is
automatically read before the lower byte.
Figure 16.2 shows the data flow when reading from ADDR.
<Reading the upper byte>
CPU
(H'AA)
Bus interface
Module data bus
<Reading of the lower byte>
CPU
(H'40)
Bus interface
ADDRnH
(H'AA)
TEMP
(H'40)
ADDRnL
(H'40)
Module data bus
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
Figure 16.2 ADDR Access Operation (During Reading of (H'AA40))
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