SH7040 Datasheet, PDF (414/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Complementary PWM Mode Output Protection Function: Complementary PWM mode output
has the following protection functions.
• Register and counter miswrite prevention function
With the exception of the buffer registers, which can be rewritten at any time, access by the
CPU can be enabled or disabled for the mode registers, control registers, compare registers,
and counters used in complementary PWM mode by means of bit 13 in the bus controller’s bus
control register 1 (BCR1). The registers and counters concerned are listed in table 12.3.
This function enables miswriting due to CPU runaway to be prevented by disabling CPU
access to the mode registers, control registers, and counters.
• Halting of PWM output by external signal
The 6-phase PWM output pins can be set automatically to the high-impedance state by
inputting specified external signals. There are four external signal input pins.
See section 12.9, Port Output Enable (POE), for details.
• Halting of PWM output when oscillator is stopped
If it is detected that the clock input to the SH7040 chip has stopped, the 6-phase PWM output
pins automatically go to the high-impedance state. The pin states are not guaranteed when the
clock is restarted.
See section 4.4, Oscillator Halt Function, for details.
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