SH7040 Datasheet, PDF (438/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.7.13 Reset Sync PWM Mode Buffer Operation and Compare Match Flag
When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR4 to
0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR4 is set
to 1.
In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA
and BFB bit settings of TMDR3. For example, if the BFA bit of TMDR3 is set to 1, TGR3C
functions as the buffer register for TGR3A. At the same time, TGR4C functions as the buffer
register for TRG4A.
When setting buffer operation for reset sync PWM mode, take particular care, since compare-
match flag TGFC bit and TGFD bit operations differ with TSR3 and TSR4.
The TGFC bit and TGFD bit of TSR3 are not set when TGR3C and TGR3D are operating as
buffer registers. On the other hand, TSR4’s TGFC and TGFD bits are set even when TGR4C and
TGR4D are operating as buffer registers.
When buffer operation has been set for reset sync PWM mode, set the timer interrupt enable
register’s (TIER4) TGIEC and TGIED bits to 0, to prohibit interrupt output.
Figure 12.87 shows an example of operations for TGR3, TGR4, TIOC3, and TIOC4, with
TMDR3’s BFA and BFB bits set to 1, and TMDR4’s BFA and BFB bits set to 0.
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