SH7040 Datasheet, PDF (302/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

The reload function can be executed whether the transfer data size is 8, 16, or 32 bits.
DMATCR2, which specifies the number of transfers, is decremented by 1 at the end of every
single-transfer-unit transfer, regardless of whether the reload function is on or off. Therefore,
when using the reload function in the on state, a multiple of 4 must be specified in DMATCR2.
Operation will not be guaranteed if any other value is set. Also, the counter which counts the
occurrence of four transfers for address reloading is reset by clearing of the DME bit in DMAOR
or the DE bit in CHCR2, setting of the transfer end flag (the TE bit in CHCR2), NMI input, and
setting of the AE flag (address error generation in DMAC transfer), as well as by a reset and in
software standby mode, but SAR2, DAR2, DMATCR2, and other registers are not reset.
Consequently, when one of these sources occurs, there is a mixture of initialized counters and
uninitialized registers in the DMAC, and incorrect operation may result if a restart is executed in
this state. Therefore, when one of the above sources, other than TE setting, occurs during use of
the address reload function, SAR, DAR2, and DMATCR2 settings must be carried out before re-
execution.
11.3.12 DMA Transfer Ending Conditions
The DMA transfer ending conditions vary for individual channels ending and for all channels
ending together.
Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when
the value of the channel’s DMA transfer count register (DMATCR) is 0, or when the DE bit of the
channel’s CHCR is cleared to 0.
• When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's
DMA transfer ends, the transfer end flag bit (TE) is set in the CHCR. If the IE (interrupt
enable) bit has been set, a DMAC interrupt (DEI) is requested of the CPU.
• When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the
channel’s CHCR. The TE bit is not set when this happens.
Conditions for Ending All Channels Simultaneously: Transfers on all channels end when the
NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in the DMAOR, or when the DME
bit in the DMAOR is cleared to 0.
• When the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address
error occurs, the NMIF or AE bit is set to 1 in the DMAOR and all channels stop their
transfers. The DMAC obtains the bus rights, and if these flags are set to 1 during execution of
a transfer, DMAC halts operation when the transfer processing currently being executed ends,
and transfers the bus right to the other bus master. Consequently, even if the NMIF or AE bits
are set to 1 during a transfer, the DMA source address register (SAR), designation address
register (DAR), and transfer count register (TCR) are all updated. The TE bit is not set. To
resume the transfers after NMI interrupt or address error processing, clear the appropriate flag
bit to 0. To avoid restarting a transfer on a particular channel, clear its DE bit to 0.
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