SH7040 Datasheet, PDF (599/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

15.4.9 A/D Conversion Time
The high speed A/D converter has an on-chip sample and hold circuit. The high speed A/D
converter samples the input at time t_D after the ADST bit is set to 1, and then starts the conversion.
The A/D conversion time t_CONV is the sum of the conversion start delay time t_D, the input sampling
time t_SPL, and the operating time t_CP. This conversion time is not a set value, but is decided by the
t_D ADCSR write timing, or the timer conversion start trigger generation timing.
Figure 15.13 shows an example of A/D conversion timing. Table 15.7 lists A/D conversion times.
φ
Address
Write signal
ADST
Sampling
timing
ADF
t_D
t_SPL
t_CP
t_CONV
t _D: A/D conversion start delay time
t _SPL: Input sampling time
t _CONV: A/D conversion time
t _CP: Operation time
Figure 15.13 A/D Conversion Timing
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