SH7040 Datasheet, PDF (154/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Interrupt acceptance
1
3
5 + m1 + m2 + m3
3 m1 m2 1 m3 1
IRQ
Instruction (instruction
replaced by interrupt
exception processing)
Overrun fetch
Interrupt service routine
start instruction
F DE E MMEME E
F
FDE
F: Instruction fetch (instruction fetched from memory where program is stored).
D: Instruction decoding (fetched instruction is decoded).
E: Instruction execution (data operation and address calculation is performed
according to the results of decoding).
M: Memory access (data in memory is accessed).
Figure 6.5 Pipeline when an IRQ Interrupt is Accepted
6.6 Data Transfer with Interrupt Request Signals
The following data transfers can be done using interrupt request signals:
• Activate DMAC only, without generating CPU interrupt
• Activate DTC only, CPU interrupts according to DTC settings
Among interrupt sources, those designated as DMAC activating sources are masked and not input
to the INTC. The masking condition is listed below:
Mask condition = DME • (DE0 • source selection 0 + DE1 × source selection 1 + DE2 •
source selection 2 + DE3 • source selection 3)
The INTC masks CPU interrupts when the corresponding DTE bit is a 1. The DTE clear condition
and interrupt source flag clear condition are listed below.
DTE clear condition = DTC transfer end • DTECLR
Interrupt source flag clear condition = DTC transfer end • DTECLR + DMAC transfer end
Where: DTECLR = DISEL + counter 0.
Figure 6.6 shows a control block diagram.
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