SH7040 Datasheet, PDF (462/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

(11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in Complementary PWM Mode: Figure 12.106 shows an explanatory diagram of the
case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM
mode after re-setting.
MTU output
1
2
3
4
RESET TMDR TOER TIOR
(PWM1) (1) (1 init
0 out)
5
PFC
(MTU)
6
TSTR
(1)
7
8
9
10
11
12
13
14
15
16
17
Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER
occurs (PORT) (0) (normal) (0 init (disabled) (0)
(CPWM) (1)
0 out)
18
PFC
(MTU)
19
TSTR
(1)
TIOC3A
TIOC3B
• Not initialized (TIOC3B)
TIOC3D
Port output
PE8
PE9
• Not initialized (TIOC3D)
High-Z
High-Z
PE11
High-Z
Figure 12.106 Error Occurrence in PWM Mode 1, Recovery in Complementary
PWM Mode
1 to 10 are the same as in figure 12.102.
11. Set normal mode for initialization of the normal mode waveform generation section.
12. Initialize the PWM mode 1 waveform generation section with TIOR.
13. Disable operation of the PWM mode 1 waveform generation section with TIOR.
14. Disable channel 3 and 4 output with TOER.
15. Select the complementary PWM output level and cyclic output enabling/disabling with
TOCR.
16. Set complementary PWM.
17. Enable channel 3 and 4 output with TOER.
18. Set MTU output with the PFC.
19. Operation is restarted by TSTR.
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