SH7040 Datasheet, PDF (229/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

10.4.3 Wait State Control
Wait state insertion during DRAM space access is controlled by setting the TPC, RCD, DWW1,
DWW0, DWR1, and DWR0 bits of the DCR. TPC and RCD are common to both reads and
writes. The timing with waits inserted is shown in figures 10.8 through 10.11. External waits can
be inserted at the time of software waits 2, 3. The sampling location is the same as that of ordinary
space: at one cycle before the T_c2 cycle clock rise. Wait cycles are extended by external waits.
CK
Address
Write
Data
RAS
CASx
RDWR
T_p
T_r
T_c1
T_cw1
T_c2
Row
Column
Read
Data
RAS
CASx
RDWR
Figure 10.8 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, One Wait)
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