SH7040 Datasheet, PDF (237/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

10.5 Address/Data Multiplex I/O Space Access
When the BCR1 register IOE bit is set to 1, the D15–D0 pins can be used for multiplexed
address/data I/O for the CS3 space. Consequently, peripheral LSIs requiring address/data
multiplexing can be directly connected to this LSI.
Address/data multiplex I/O space bus width is selected by the A14 bit, and is 8 bit when A14 = 0
and 16 bit when A14 = 1.
10.5.1 Basic Timing
When the IOE bit of the BCR1 is set to 1, CS3 space becomes address/data multiplex I/O space.
When this space is accessed, addresses and data are multiplexed. When the A14 address bit is 0,
the bus size becomes 8 bit and addresses and data are input and output through the D7–D0 pins.
When the A14 address bit is 1, the bus size becomes 16 bit and address output and data I/O occur
through the D15–D0 pins. Access for the address/data multiplex I/O space is controlled by the
AH, RD, and WRx signals.
Address/data multiplex I/O space accesses are done after a 3-cycle (fixed) address output, as an
ordinary space type access (figure 10.17).
T_a1
T_a2
T_a3
T_a4
T₁
T₂
CK
Address
CS3
AH
Read
RD
Data
Write
WRx
Data
Address output
Address output
Data input
Data output
Figure 10.17 Address/Data Multiplex I/O Space Access Timing (No Waits)
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