SH7040 Datasheet, PDF (488/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bit 9—Output Level Compare Enable (OCE): This bit enables the start of output level
comparisons. When setting this bit, pay special attention to the output pin combinations shown
in table 12.19. When 0 is output, the OSF bit is set to 1 at the same time this bit is set, and
output goes to high impedance. Accordingly, bits 15–11 and bit 9 of the port E data register
(PEDR) are set to 1. For the MTU output comparison, set the bit to 1 after setting the MTU’s
output pins with the PFC. Set this bit only when using pins as outputs.
When the OCE bit is set to 1, if OIE = 0 a high-impedance request will not be issued even if
OSF is set to 1. Therefore, in order to have a high-impedance request issued according to the
result of the output comparison, the OIE bit must be set to 1. When OCE = 1 and OIE = 1, an
interrupt request will be generated at the same time as the high-impedance request; however,
this interrupt can be masked by means of an interrupt controller (INTC) setting.
Bit 9: OCE
0
1
Description
Output level compare disabled (initial value)
Output level compare enabled; makes an output high impedance request
when OSF = 1.
• Bit 8—Output Short Interrupt Enable (OIE): Makes interrupt requests when the OSF bit of the
OCSR is set.
Bit 8: OIE
0
1
Description
Interrupt requests disabled (initial value)
Interrupt requests enabled
• Bits 7–0—Reserved: Always read as 0, and cannot be modified.
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