SH7040 Datasheet, PDF (558/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Figures 14.14 and 14.15 show examples of SCI receive operation using a multiprocessor format.
Serial
data
Start Data
1 _{bit (ID1)}
0 D0 D1
Stop Start Data
MPB bit bit (data 1)
D7 1 1 0 D0 D1
Stop
MPB bit
1
D7 0 1 Idling
(marking)
MPB
MPIE
RDRF
RDR
value
ID1
RxI interrupt request
(multiprocessor
interrupt), MPIE = 0
RxI interrupt handler
reads data in RDR
and clears RDRF to 0
Not station’s
ID, so MPIE is
set to 1 again
No RxI interrupt,
RDR maintains
state
Figure 14.14 SCI Receive Operation (ID Does Not Match)
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