SH7040 Datasheet, PDF (173/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

8.1.3 Register Configuration
The DTC has five registers in memory used for storing transfer data: DTMR, DTCR, DTSAR,
DTDAR, and DTIAR. It is controlled by the three registers DTER (DTEA–DTEE), DTCSR, and
DTBR. The register configurations are listed in table 8.1.
Table 8.1 Register Configuration^*1
Name
Abbr. R/W Initial Value Address
Access Size
DTC mode register
DTMR —^*2 Undefined —^*2
—^*2
DTC source address register
DTSAR —^*2 Undefined —^*2
—^*2
DTC destination address register DTDAR —^*2 Undefined —^*2
—^*2
DTC initial address register
DTIAR —^*2 Undefined —^*2
—^*2
DTC transfer count register A
DTCRA —^*2 Undefined —^*2
—^*2
DTC transfer count register B
DTCRB —^*2 Undefined —^*2
—^*2
DTC enable register A
DTEA R/W H'00
H'FFFF8700 8, 16, 32
DTC enable register B
DTEB R/W H'00
H'FFFF8701 8, 16, 32
DTC enable register C
DTEC R/W H'00
H'FFFF8702 8, 16, 32
DTC enable register D
DTED R/W H'00
H'FFFF8703 8, 16, 32
DTC enable register E
DTEE R/W H'00
H'FFFF8704 8, 16, 32
DTC control/status register
DTCSR R/(W)^*3 H'0000
H'FFFF8706 8, 16, 32
DTC information base register DTBR R/W Undefined H'FFFF8708 16, 32
Notes: *1 DTC registers cannot be accessed by DMAC/DTC.
*2 DTC internal registers cannot be directly accessed.
*3 Only a 0 write after a 1 read is possible for the NMIF, AE bits of the DTCSR.
8.2 Register Description
8.2.1 DTC Mode Register (DTMR)
The DTC mode register (DTMR) is a 16-bit register that controls the DTC operation mode. The
contents of this register is located in memory.
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