SH7040 Datasheet, PDF (151/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Program
execution state
Interrupt?
No
Yes
NMI?
No
Yes
User break?
No
IRQOUT = low level^*1
Save SR to stack
Save PC to stack
Copy accept-interrupt
level to I3 to I0
IRQOUT = high level^*2
Yes
Yes
Level 15 No
interrupt?
Yes
I3 to I0 ≤
level 14?
No _Yes
Level 14
interrupt?
Yes
I3 to I0 ≤
level 13?
No
Level 1 ^No
interrupt?
Yes
No Yes
I3 to I0 =
level 0?
Reads exception
No
vector table
Branches to exception
service routine
I3 to I0: Interrupt mask bits of status register
Notes: *1
*2
IRQOUT is the same signal as the interrupt request signal to the CPU (see
figure 6.1). Thus, it is output when there is a higher priority interrupt request
than the one in the I3 to I0 bits of the SR.
When the accepted interrupt is sensed by edge, the IRQOUT pin becomes
high level at the point when the CPU starts interrupt exception processing
instead of instruction execution (before SR is saved to the stack).
If the interrupt controller has accepted another interrupt with a higher priority
and has output an interrupt request to the CPU, the IRQOUT pin will remain
low level.
Figure 6.3 Interrupt Sequence Flowchart
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