SH7040 Datasheet, PDF(376/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (376/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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Table 12.7 lists the combinations of PWM output pins and registers.

Table 12.7 Combinations of PWM Output Pins and Registers

Output Pin

Channel

Register

PWM Mode 1

PWM Mode 2

0 (AB pair)

TGR0A

TGR0B

TIOC0A

TIOC 0A

TIOC 0B

0 (CD pair)

TGR0C

TGR0D

TIOC0C

TIOC 0C

TIOC 0D

1

TGR1A

TIOC1A

TIOC 1A

TGR1B

TIOC 1B

2

TGR2A

TIOC2A

TIOC 2A

TGR2B

TIOC 2B

3 (AB pair)

TGR3A

TGR3B

TIOC3A

Setting not possible

3 (CD pair)

TGR3C

TGR3D

TIOC3C

4 (AB pair)

TGR4A

TGR4B

TIOC4A

4 (CD pair)

TGR4C

TGR4D

TIOC4C

Note: PWM output of the period setting TGR is not possible in PWM mode 2.

Procedure for Selecting the PWM Mode (Figure 12.24):

1. Set bits TPSC2âTPSC0 in the TCR to select the counter clock source. At the same time, set

bits CKEG1 and CKEG0 in the TCR to select the desired edge of the input clock.

2. Set bits CCLR2âCCLR0 in the TCR to select the TGR to be used as a counter clear source.

3. Set the period in the TGR selected in step 2, and the duty cycle in another TGR.

4. Using the timer I/O control register (TIOR), set the TGR selected in step 3 to act as an output

compare register, and select the initial value and output value.

5. Set the MD3âMD 0 bits in TMDR to select the PWM mode.

6. Set the CST bit in the TSTR to 1 to let the TCNT start counting.

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