SH7040 Datasheet, PDF (227/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

10.4 DRAM Access
10.4.1 DRAM Direct Connection
When address space A31–A24 = H'01 has been accessed, the corresponding space becomes a 16-
Mbyte DRAM space, and the DRAM interface function can be used to directly connect the
SH7040 Series to DRAM.
Row address and column address are always multiplexed for DRAM space. The amount of row
address multiplexing can be selected as from 9 to 12 bits by setting the AMX1 and AMX0 bits of
the DCR.
Table 10.5 AMX Bits and Address Multiplex Output
AMX1
0
0
1
1
AMX0
0
1
0
1
Shift
Amount
9 bit
10 bit
11 bit
12 bit
Row Address
Output Pins Output
Address
A21–A15 A21–A15
A14–A0
A23–A9
A21–A14 A21–A14
A13–A0
A23–A10
A21–A13 A21–A13
A12–A0
A23–A11
A21–A12 A21–A12
A11–A0
A23–A12
Column Address
Output
Address
Output
Pins
A21–A0
A21–A0
A21–A0
A21–A0
A21–A0
A21–A0
A21–A0
A21–A0
In addition to ordinary read and write accesses, burst mode access using high speed page mode is
supported.
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