SH7040 Datasheet, PDF (347/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.2.5 Timer Status Register (TSR)
The timer status register (TSR) is an 8-bit register that indicates the status of each channel. The
MTU has five TSR registers, one each for channel. TSR is initialized to H'C0 by a power-on reset
or by standby mode. This register is not initialized by a manual reset.
Channel 0: TSR0:
Bit: 7
6
5
4
—
—
—
TCFV
Initial value: 1
1
0
0
R/W: R
R
R
R/(W)^*
Note: * Only 0 writes to clear the flags are possible.
3
TGFD
0
R/(W)^*
2
TGFC
0
R/(W)^*
1
TGFB
0
R/(W)^*
0
TGFA
0
R/(W)^*
Channels 1, 2: TSR1, TSR2:
Bit: 7
6
5
4
3
TCFD — TCFU TCFV —
Initial value: 1
1
0
0
0
R/W: R
R R/(W)^* R/(W)^* R
Note: * Only 0 writes to clear the flags are possible.
2
1
0
—
TGFB TGFA
0
0
0
R
R/(W)^* R/(W)^*
Channels 3, 4: TSR3, TSR4:
Bit: 7
6
5
4
TCFD —
—
TCFV
Initial value: 1
1
0
0
R/W: R
R
R
R/(W)^*
Note: * Only 0 writes to clear the flags are possible.
3
TGFD
0
R/(W)^*
2
TGFC
0
R/(W)^*
1
TGFB
0
R/(W)^*
0
TGFA
0
R/(W)^*
• Bit 7—Count Direction Flag (TCFD): This status flag indicates the count direction of the
channel 1, 2, 3, 4 TCNT counters.
This bit is reserved in channel 0. This bit always reads as 1. The write value should always be
1.
Bit 7: TCFD
0
1
Description
TCNT counts down
TCNT counts up (initial value)
• Bit 6—Reserved: This bit always reads as 1. The write value should always be 1.
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