SH7040 Datasheet, PDF (541/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

14.3.2 Operation in Asynchronous Mode
In the asynchronous mode, each transmitted or received character begins with a start bit and ends
with a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full duplex communication
is possible. The transmitter and receiver are both double buffered, so data can be written and read
while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
Figure 14.2 shows the general format of asynchronous serial communication. In asynchronous
serial communication, the communication line is normally held in the marking (high) state. The
SCI monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and stop bit (high), in that order.
When receiving in the asynchronous mode, the SCI synchronizes on the falling edge of the start
bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit
rate. Receive data is latched at the center of each bit.
1
(LSB)
Idling (marking state)
(MSB)
1
Serial _{0 D0}
data
Start
bit
1 bit
D1 D2 D3 D4 D5 D6
Transmit/receive data
7 or 8 bits
D7 0/1 1 1
Parity Stop
bit
bit
1 or 1 or
no bit 2 bits
One unit of communication data (characters or frames)
Figure 14.2 Data Format in Asynchronous Communication (Example: 8-bit Data with
Parity and Two Stop Bits)
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