SH7040 Datasheet, PDF (379/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

100% Duty Cycle: Figure 12.28 shows an example of a 100% duty cycle PWM waveform output
in PWM mode.
In PWM mode, when setting cycle = duty cycle the output waveform does not change, nor is there
a change of waveform for the first pulse immediately after clearing the counter.
TCNT value
TGRA
TGRB rewrite
TGRB
TIOCA
Output does not change if period register and duty
cycle register compare matches occur simultaneously
TGRB rewrite
100% duty cycle
TGRB rewrite
Time
TCNT value
TGRA
TGRB rewrite
Output does not change if period register and duty
cycle register compare matches occur simultaneously
TGRB rewrite
TGRB
TIOCA
100% duty cycle
TGRB rewrite
Time
0% duty cycle
Figure 12.28 PWM Mode Operation Example (100% Duty Cycle)
12.4.7 Phase Counting Mode
The phase counting mode detects the phase differential of two external clock inputs and counts the
TCNT counter up or down. This mode can be set for channels 1 and 2.
When set in the phase counting mode, an external clock is selected for the counter input clock,
regardless of the settings of the TPSC2–TPSC0 bits of TCR or the CKEG1 and CKEG0 bits.
TCNT also becomes an up/down counter. Since the TCR CCLR1/CCLR0 bits, TIOR, TIER, and
TGR functions are all enabled, input capture and compare-match functions and interrupt sources
can be used.
When the TCNT counter is incrementing, an overflow sets the TSR register TCFV (overflow
flag). When it is decrementing, an underflow sets the TCFU (underflow flag).
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