SH7040 Datasheet, PDF (490/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.11.2 Output-Level Compare Operation
Figure 12.127 shows an example of the output-level compare operation for the combination of
PE09/TIOC3B and PE11/TIOC3D. The operation is the same for the other pin combinations.
CK
PE09/
TIOC3B
PE11/
TIOC3D
0 level overlapping detected
High impedance state
Figure 12.127 Output-Level Detection Operation
12.11.3 Release from High-Impedance State
High-current pins that have entered high-impedance state due to input-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing all of
the bit 12–15 (POE0F–POE3F) flags of the ICSR. High-current pins that have become high-
impedance due to output-level detection can be released either by returning them to their initial
state with a power-on reset, or by first clearing bit 9 (OCE) of the OCSR to disable output-level
compares, then clearing the bit 15 (OSF) flag. However, when returning from high-impedance
state by clearing the OSF flag, always do so only after outputting a high level from the high-
current pins (TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D). High-level outputs
can be achieved by setting the MTU internal registers. See section 12.2, MTU Register
Descriptions, for details.
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