SH7040 Datasheet, PDF (8/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Section
11.2.3 DMA
Transfer Count
Registers 0–3
(DMATCR0–
DMATCR3)
11.2.4 DMA
Channel Control
Registers 0–3
(CHCR0–CHCR3)
Page
220
221
224
11.2.5 DMAC
226
Operation Register
(DMAOR)
227
11.3.3 Channel
233
Priority
Figure 11.3 Round
Robin Mode
12.4.5 Cascade
337
Connection Mode
Figure 12.23
Cascade Connection
Operation Example
(Phase Counting
Mode)
12.4.9
373
Complementary
PWM Mode
Figure 12.55
Example of Output
Phase Switching by
External Input (1)
Description
Description amended
The data for the upper 8 bits of a DMATCR is 0
when read.
Description amended
• Bits 31–21—Reserved bits: Data are 0
value always be 0.
when read. The write
Description amended
• Bit 7—Reserved bits: Data is 0
always be 0.
when read. The write value
Description amended
• Bits 15–10—Reserved bits: Data are 0
value always be 0.
when read. The write
Description amended
• Bits 7–3—Reserved bits: Data are 0
value always be 0.
when read. The write
Figure amended
Channel 0 is given the lowest
priority.
Figure amended
TCLKC
TCLKD
Figure amended
When BDC = 1, N = 0, P = 0, FB = 0, output active level = high