SH7040 Datasheet, PDF (103/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 2.13 Arithmetic Operation Instructions
Instruction
ADD
Rm,Rn
ADD
#imm,Rn
ADDC Rm,Rn
ADDV Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PL Rn
CMP/PZ Rn
CMP/STR Rm,Rn
DIV1 Rm,Rn
DIV0S Rm,Rn
DIV0U
Instruction Code
0011nnnnmmmm1100
0111nnnniiiiiiii
0011nnnnmmmm1110
0011nnnnmmmm1111
10001000iiiiiiii
0011nnnnmmmm0000
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
0011nnnnmmmm0111
0100nnnn00010101
0100nnnn00010001
0010nnnnmmmm1100
0011nnnnmmmm0100
0010nnnnmmmm0111
0000000000011001
Operation
Rn + Rm → Rn
Rn + imm → Rn
Rn + Rm + T → Rn,
Carry → T
Rn + Rm → Rn,
Overflow → T
If R0 = imm, 1 → T
Execu-
tion
Cycles
1
1
1
1
1
If Rn = Rm, 1 → T
1
If Rn≥Rm with unsigned 1
data, 1 → T
If Rn ≥ Rm with signed 1
data, 1 → T
If Rn > Rm with
1
unsigned data, 1 → T
If Rn > Rm with signed 1
data, 1 → T
If Rn > 0, 1 → T
1
If Rn ≥ 0, 1 → T
1
If Rn and Rm have
1
an equivalent byte,
1→T
Single-step division
1
(Rn/Rm)
MSB of Rn → Q, MSB 1
of Rm → M, M ^ Q → T
0 → M/Q/T
1
T Bit
—
—
Carry
Overflow
Comparison
result
Comparison
result
Comparison
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Comparison
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Comparison
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Comparison
result
Comparison
result
Comparison
result
Comparison
result
Calculation
result
Calculation
result
0
65