SH7040 Datasheet, PDF (221/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bit 0—Refresh Mode (RMD): When the RFSH bit is 1, this bit selects normal refresh or self-
refresh. When the RFSH bit is 1, self-refresh mode is entered immediately after the RMD bit is
set to 1. When RMD is cleared to 0, a CAS-before-RAS refresh is performed at the interval set
in the refresh time constant register (RTCNT).
When set for self-refresh, the SH7040 Series enters self-refresh mode immediately unless it is
in the middle of a DRAM access. If it is, it enters self-refresh mode when the access ends.
Refresh requests from the interval timer are ignored in self-refresh mode.
Bit 0 (RMD)
0
1
Description
CAS-before-RAS refresh (initial value)
Self-refresh
10.2.7 Refresh Timer Counter (RTCNT)
RTCNT is a 16-bit read/write register that is used as an 8-bit up counter for refreshes or generating
interrupt requests.
RTCNT counts up with the clock selected by the CKS2–CKS0 bits of the RTCSR. RTCNT values
can always be read/written by the CPU. When RTCNT matches RTCOR, RTCNT is cleared to
H'0000 and the CMF flag of the RTCSR is set to 1. If the RFSH bit of RTCSR is 1 and the RMD
bit is 0 at this time, a CAS-before-RAS refresh is performed. Additionally, if the CMIE bit of
RTCSR is a 1, a compare match interrupt (CMI) is generated.
Bits 15–8 are reserved and play no part in counter operation. They are always read as 0.
RTCNT is initialized by power-on resets H'0000, but is not initialized by manual resets or
software standbys.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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