SH7040 Datasheet, PDF (167/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

2. Register settings:
Conditions set:
UBARH = H'0015
UBARL = H'389C
UBBR = H'0058
Address: H'0015389C
Bus cycle: CPU, instruction fetch, write
(operand size not included in conditions)
A user break interrupt does not occur because the instruction fetch cycle is not a write cycle.
3. Register settings:
Conditions set:
UBARH = H'0003
UBARL = H'0147
UBBR = H'0054
Address: H'00030147
Bus cycle: CPU, instruction fetch, read
(operand size not included in conditions)
A user break interrupt does not occur because the instruction fetch was performed for an even
address. However, if the first instruction fetch address after the branch is an odd address set by
these conditions, user break interrupt exception processing will be done after address error
exception processing.
7.4.2 Break on CPU Data Access Cycle
1. Register settings:
Conditions set:
UBARH = H'0012
UBARL = H'3456
UBBR = H'006A
Address: H'00123456
Bus cycle: CPU, data access, write, word
A user break interrupt occurs when word data is written into address H'00123456.
2. Register settings:
Conditions set:
UBARH = H'00A8
UBARL = H'0391
UBBR = H'0066
Address: H'00A80391
Bus cycle: CPU, data access, read, word
A user break interrupt does not occur because the word access was performed on an even address.
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