SH7040 Datasheet, PDF (25/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

6.2.3 IRQ Interrupts....................................................................................................... 102
6.2.4 On-Chip Peripheral Module Interrupts................................................................. 103
6.2.5 Interrupt Exception Vectors and Priority Rankings ............................................. 103
6.3 Description of Registers..................................................................................................... 108
6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH)................................................... 108
6.3.2 Interrupt Control Register (ICR) .......................................................................... 109
6.3.3 IRQ Status Register (ISR) .................................................................................... 110
6.4 Interrupt Operation............................................................................................................. 112
6.4.1 Interrupt Sequence ................................................................................................ 112
6.4.2 Stack after Interrupt Exception Processing........................................................... 114
6.5 Interrupt Response Time.................................................................................................... 114
6.6 Data Transfer with Interrupt Request Signals ................................................................... 116
6.6.1 Handling DTC Activating and CPU Interrupt Sources,
but Not DMAC Activating Sources ..................................................................... 117
6.6.2 Handling DMAC Activating Sources but Not CPU Interrupt
or DTC Activating Sources .................................................................................. 118
6.6.3 Handling DTC Activating Sources but Not CPU Interrupt
or DMAC Activating Sources .............................................................................. 118
6.6.4 Treating CPU Interrupt Sources but Not DTC
or DMAC Activating Sources .............................................................................. 118
Section 7 User Break Controller (UBC) ..................................................................... 119
7.1 Overview............................................................................................................................ 119
7.1.1 Features................................................................................................................. 119
7.1.2 Block Diagram...................................................................................................... 119
7.1.3 Register Configuration ......................................................................................... 120
7.2 Register Descriptions......................................................................................................... 121
7.2.1 User Break Address Register (UBAR)................................................................. 121
7.2.2 User Break Address Mask Register (UBAMR) ................................................... 122
7.2.3 User Break Bus Cycle Register (UBBR).............................................................. 123
7.3 Operation ........................................................................................................................... 126
7.3.1 Flow of the User Break Operation ....................................................................... 126
7.3.2 Break on On-Chip Memory Instruction Fetch Cycle ........................................... 128
7.3.3 Program Counter (PC) Values Saved ................................................................... 128
7.4 Use Examples..................................................................................................................... 128
7.4.1 Break on CPU Instruction Fetch Cycle ................................................................ 128
7.4.2 Break on CPU Data Access Cycle........................................................................ 129
7.4.3 Break on DMA/DTC Cycle .................................................................................. 130
7.5 Cautions on Use................................................................................................................. 130
7.5.1 On-Chip Memory Instruction Fetch ..................................................................... 130
7.5.2 Instruction Fetch at Branches ............................................................................... 130
7.5.3 Contention between User Break and Exception Handling ................................... 131
7.5.4 Break at Non-Delay Branch Instruction Jump Destination .................................. 131
iii