SH7040 Datasheet, PDF (180/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bit 10—NMI Flag Bit (NMIF): Indicates that an NMI interrupt has occurred. When the NMIF
bit is set, DTC transfers are not allowed even if the DTER bit is set to 1. If, however, a transfer
has already started with the NMIM bit of the DTMR set to 1, execution will continue until that
transfer ends. To clear the NMIF bit, read the 1 from it, then write a 0.
The NMIF bit is initialized to 0 by power-on resets and in standby mode.
Bit 10 (NMIF)
0
1
Description
No NMI interrupts (initial value)
(Clear condition) Write a 0 after reading the NMIF bit
NMI interrupt has been generated
• Bit 9—Address Error Flag (AE): Indicates that an address error by the DTC has occurred.
When the AE bit is set, DTC transfers are not allowed even if the DTER bit is set to 1. To clear
the AE bit, read the 1 from it, then write a 0.
The AE bit is initialized to 0 by power-on resets and in standby mode.
Bit 9 (AE)
0
1
Description
No address error by the DTC (initial value)
(Clear condition) Write a 0 after reading the AE bit
An address error by the DTC occurred
• Bit 8—DTC Software Activation Enable Bit (SWDTE): This bit enables/disables DTC
activation by software.
The AE bit is initialized to 0 by resets and standby mode. For details, see section 8.3.2,
Activating Sources.
Bit 8 (SWDTE)
0
1
Description
DTC activation by software disabled (initial value)
DTC activation by software enabled
• Bits 7–0—Software Activation Vectors 7–0 (DTVEC7–DTVEC0): These bits set the DTC
vector addresses for DTC activation by software. A vector address is calculated as H'0400 +
DTVEC[7:0]. Always specify 0 for DTVEC0. 8 bits are available, so you can specify values
H'00 (0)–H'FE (254).
142