SH7040 Datasheet, PDF (734/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 22.4 Flash Memory Erase Blocks
Block (size)
EB0 (32kB)
EB1 (32kB)
EB2 (32kB)
EB3 (32kB)
EB4 (32kB)
EB5 (32kB)
EB6 (32kB)
EB7 (28kB)
EB8 (1kB)
EB9 (1kB)
EB10 (1kB)
EB11 (1kB)
Addresses
H'000000–H'007FFF
H'008000–H'00FFFF
H'010000–H'017FFF
H'018000–H'01FFFF
H'020000–H'027FFF
H'028000–H'02FFFF
H'030000–H'037FFF
H'038000–H'03EFFF
H'03F000–H'03F3FF
H'03F400–H'03F7FF
H'03F800–H'03FBFF
H'03FC00–H'03FFFF
22.5.5 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'0000 by a power-on reset. It is
not initialized in software standby mode. RAMER settings should be made in user mode or user
program mode. (For details, see the description of the BSC.)
Flash memory area divisions are shown in table 22.5. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
— RAMS RAM1 RAM0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
• Bits 15–3—Reserved bits: These bits are always read as 0.
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