SH7040 Datasheet, PDF (159/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 7.1 Register Configuration
Name
Abbr.
User break address register H
UBARH
User break address register L
UBARL
User break address mask register H UBAMRH
User break address mask register L UBAMRL
User break bus cycle register
UBBR
Initial
R/W Value Address
Access
Size
R/W H'0000 H'FFFF8600 8, 16, 32
R/W H'0000 H'FFFF8602 8, 16, 32
R/W H'0000 H'FFFF8604 8, 16, 32
R/W H'0000 H'FFFF8606 8, 16, 32
R/W H'0000 H'FFFF8608 8, 16, 32
7.2 Register Descriptions
7.2.1 User Break Address Register (UBAR)
The user break address register (UBAR) consists of user break address register H (UBARH) and
user break address register L (UBARL). Both are 16-bit readable/writable registers. UBARH
stores the upper bits (bits 31–16) of the address of the break condition, while UBARL stores the
lower bits (bits 15–0). Resets and hardware standbys initialize both UBARH and UBARL to
H'0000. They are not initialized in manual reset or software standby mode.
UBARH:
Bit:
UBARH
Initial value:
R/W:
15
UBA31
0
R/W
14
UBA30
0
R/W
13
UBA29
0
R/W
12
UBA28
0
R/W
11
UBA27
0
R/W
10
UBA26
0
R/W
9
UBA25
0
R/W
8
UBA24
0
R/W
Bit:
UBARH
Initial value:
R/W:
7
UBA23
0
R/W
6
UBA22
0
R/W
5
UBA21
0
R/W
4
UBA20
0
R/W
3
UBA19
0
R/W
2
UBA18
0
R/W
1
UBA17
0
R/W
0
UBA16
0
R/W
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